1. Field
Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a semiconductor device with a padless structure and a method for fabricating the same.
2. Description of the Related Art
Spacer patterning technology (SPT) may be used to form word lines of a semiconductor memory device. Generally, a semiconductor device has a cell region and a peripheral circuit region. The word lines have a structure where the cell region extends from the peripheral circuit region, and the peripheral circuit region includes a region where pads are formed that electrically connect conductive lines (for example, metal wirings) and the word lines. An example of the region where pads are formed is a decoder region. In this configuration, bridge fail may result because the decoder region always has an insufficient patterning margin due to the structural shape. Further, with the decrease in the design rules, the patterning margin may be even more reduced when a double spacer patterning technology (double-SPT) is applied instead of a single spacer patterning technology (single-SPT). Hereafter, features of a semiconductor device in accordance with the conventional technology will be described in detail with reference to the accompanying drawings.
FIGS. 1A to 1D are plane views illustrating a method for fabricating a semiconductor device in accordance with the conventional technology, and FIGS. 2A to 2D are cross-sectional views taken along the line I-I′ illustrated in FIGS. 1A to 1D. Further, FIGS. 3A to 3C are images illustrating features of a semiconductor device in accordance with the conventional technology.
As illustrated in FIGS. 1A and 2A, a conductive layer 12 is formed on a substrate 11 having a first region and a second region. In this example, the first region is the cell region and the second region is the peripheral circuit region including a decoder region where the pads are formed.
Next, a sacrificial pattern 13 is formed on the conductive layer 12, and a first mask pattern 14 is formed on sidewalls of the sacrificial pattern 13. Subsequently, the sacrificial pattern 13 is removed.
As illustrated in FIGS. 1B and 2B, second mask patterns 15 are formed on the conductive layer 12 around first mask patterns 14 by using a PAD mask.
As illustrated in FIGS. 1C and 2C, the conductive layer 12 is etched using the first and second mask patterns 14 and 15 as an etch mask to form pads 12B in the second region while forming conductive lines 12A in the first and second regions. After etching the conductive layer 12, the first and second mask patters 14 and 15 are removed.
As illustrated in FIGS. 1D and 2D, the conductive lines 12A between the pads 12B are etched using a cut mask to separate adjacent conductive lines 12A.
However, in the conventional technology, the first mask pattern 14 formed in the second region is formed with a 90° bend from the extending direction of the first mask pattern 14 to provide a space where the pad 12B is formed. Due to the bent structural characteristics, a pattern is broken at the 90° bend since a margin for a photolithography process is insufficient (see FIG. 3A). Also due to the bent structural characteristics, securing critical dimension uniformity (CDU) (see FIG. 3B) may be difficult, and a bridge is generated between adjacent patterns (see FIG. 3C) as illustrated in FIGS. 3A to 3C.
In addition, the semiconductor device in accordance with the conventional technology, the pads 12B are uniformly disposed at the ends of the conductive lines 12A. In this case, since the semiconductor device requires a larger space corresponding to an interval between the respective pads 12B, it is difficult to reduce an area of the second region due to the pads 12B even though integration of the conductive lines 12A disposed in the first region is increased (more specifically, even though the area of the first region is reduced). More specifically, a chip size of the semiconductor device may be difficult to reduce due to the pads 12B. To reduce the area of the second region, an arrangement of the cut mask and the pad mask is complicated, which acts as a factor of reducing a margin of a conductive line 12A forming process and increasing a difficulty of subsequent processes (for example, a contact plug forming process, a metal wiring forming process) to degrade a yield of the semiconductor device.